The present invention relates to a high breakdown voltage semiconductor device.
A conventional high breakdown voltage semiconductor device is disclosed, for example, in Japanese Laid-Open Patent Publication No. 2000-12854. The high breakdown voltage semiconductor device disclosed in this publication is an insulated gate transistor. Hereinafter, a conventional insulated gate transistor will be described with reference to FIG. 12. FIG. 12 schematically shows a cross-sectional structure of a conventional insulated gate transistor.
The insulated gate transistor shown in FIG. 12 includes a p-type semiconductor substrate 1, a drain offset diffusion region 2 containing a low concentration of n-type impurities formed in the semiconductor substrate 1, a low concentration buried diffusion region 3 containing p-type impurities buried in the drain offset diffusion region 2, a drain diffusion region 4 containing a high concentration of n-type impurities located in the drain offset diffusion region 2, a source diffusion region 5 containing a high concentration of n-type impurities formed in the semiconductor substrate 1, and a diffusion region 19 for contact containing a high concentration of p-type impurities. The low concentration buried diffusion region 3 serves to promote the depletion of the drain offset diffusion region 2 when a high voltage is applied to the drain. Although not shown in FIG. 12, a part of the low concentration buried diffusion region 3 is connected to the semiconductor substrate 1. A diffusion region 20 for preventing a punch-through containing p-type impurities is formed in the semiconductor substrate 1 so as to enclose the source diffusion region 5 and the diffusion region 19 for contact. The diffusion region 20 for preventing a punch-through serves to increase the concentration of the p-type impurities between the drain offset diffusion region 2 and the source diffusion region 5, which are the active regions of an MOS transistor, to prevent a punch-through phenomenon between them.
A thin gate oxide film 6 and a thick oxide film (field oxide film) 7 are formed on the semiconductor substrate 1. A gate electrode 11 made of polysilicon is provided on a portion of the oxide film 6 or 7 on the portion between the drain offset diffusion region 2 and the source diffusion region 5. A drain polysilicon electrode 18 is formed on a portion of the oxide film 6 or 7 that is positioned on a portion between the drain offset diffusion region 2 and the drain diffusion region 4. An interlayer insulating film 8 is formed so as to cover the oxide films 6 and 7, the gate electrode 11, and the drain polysilicon electrode 18.
Metal electrodes 12, 13 and 14 are connected to the diffusion region 19 for contact, the source diffusion region 5 and the drain diffusion region 4, respectively. The metal electrode 12 is a metal electrode for a body to be connected to the p-type semiconductor substrate 1, which is a body. The metal electrode 13 is a metal electrode for a source for contact with the source diffusion region 5. The metal electrode 14 is a metal electrode for a drain for contact with the drain diffusion region 4. A surface protective film 9 is formed on the metal electrodes 12, 13 and 14 and the interlayer insulating film 8. A resin for sealing 10 is formed thereon.
In the insulated gate transistor shown in FIG. 12, a GND potential is supplied to the metal electrode 13 for a source, the metal electrode 12 for a body, and the low concentration p-type buried diffusion region 3. A positive high potential is supplied to the metal electrode 14 for a drain. A control voltage is supplied to the gate electrode 11. When a positive potential (control voltage) of a threshold or more is supplied to the gate electrode 11, an inversion from the p-type to the n-type occurs in the vicinity of the surface of the semiconductor substrate 1 immediately below the gate electrode 11, and thus a so-called channel region is generated so that the insulated gate transistor becomes conductive. The conducted current in this case flows from the drain diffusion region 4 through the drain offset diffusion region 2 and the channel region on the surface of the semiconductor substrate 1 to the source diffusion region 5. On the other hand, when the voltage of less than a threshold is supplied to the gate electrode 11, the channel region becomes small, so that the insulated gate transistor becomes non-conductive.
In this specification, maintaining the non-conductive state in a transistor is defined as xe2x80x9chaving a breakdown voltagexe2x80x9d, and maintaining the non-conductive state in a transistor at a high bias voltage (e.g., 100 V or more) is defined as xe2x80x9chaving a high breakdown voltagexe2x80x9d. The resistance value between the source and the drain while a transistor is conductive is defined as xe2x80x9cON resistancexe2x80x9d.
Next, FIG. 13 is referred to. FIG. 13 shows the potential distribution when a high voltage (600 V) is supplied to the high breakdown voltage semiconductor device (insulated gate transistor) shown in FIG. 12 at room temperature, and an equipotential line for each potential is indicated by a broken line. This potential distribution (equipotential lines) is obtained based on the results of simulation by the inventors of the present invention.
The potential distribution shown in FIG. 13 is one obtained when 0(V) is supplied to the p-type semiconductor substrate 1, the p-type low concentration buried diffusion region 3, and the n-type source diffusion region 5; 0(V) is supplied to the gate electrode 11; and 600 (V) is supplied to the n-type drain diffusion region 4. The equipotential lines in this case are shown by broken lines.
The high breakdown voltage semiconductor device shown in FIG. 12 utilizes a technique called xe2x80x9cresurfxe2x80x9d for depleting the entire drain offset diffusion region 2 to ensure an initial breakdown voltage. The principle thereof will be described below.
To operate this high breakdown voltage semiconductor device, in general, 0 (V) is supplied to the semiconductor substrate 1 and the source diffusion layer region 5, and a drain voltage necessary for operation is supplied to the metal electrode 14. When the drain voltage is gradually increased from 0 (V), while the drain voltage is low, a depletion layer stemming from the pn junction between the p-type semiconductor substrate 1 and the n-type drain offset diffusion region 2 extends into the p-type semiconductor substrate 1 and the drain offset diffusion region 2, and a depletion layer stemming from the pn junction between the p-type low concentration buried diffusion region 3 and the drain offset diffusion region 2 extends into the low concentration buried diffusion region 3 and the drain offset diffusion region 2. In FIG. 13, the concentration distribution in the vertical direction of the low concentration buried diffusion region 3 is such that the concentration of the central portion is high, and the concentration is decreased as being apart from the central portion in the upward or downward direction. Therefore, the potential in the vertical direction in the low concentration buried diffusion region 3 is distributed such that the potential is kept low in the central portion.
Furthermore, 0 (V) is set in the portion on the source side in the low concentration buried diffusion region 3, and the region extends to the drain side, so that the potential in the low concentration buried diffusion region 3 in the horizontal direction is distributed such that the potential increases in the direction from the source to the drain. Therefore, as shown in FIG. 13, the equipotential lines in the low concentration buried diffusion region 3 have a projection to the drain side.
Next, as the drain voltage is increased, the depletion layer extending from the pn junction between the semiconductor substrate 1 and the drain offset diffusion region 2 is joined with the depletion layer extending from the pn junction between the low concentration buried diffusion region 3 and the drain offset diffusion region 2. When the voltage is further increased, the drain offset diffusion region 2 is depleted except the portion near the drain diffusion region 4. When the voltage is even further increased, most of the drain offset diffusion region 2 is depleted. That is to say, high breakdown voltage characteristics can be obtained by depleting the drain offset diffusion region 2 to alleviate the concentration of the electric field in the drain offset diffusion region 2. In this structure, the low concentration buried diffusion region 3 has an effect of promoting the depletion of the drain offset diffusion region 2. Therefore, comparing this case with the case where the low concentration buried diffusion region 3 is not provided, even if the drain offset diffusion region 2 has a high concentration of impurities, the drain offset diffusion region 2 can be depleted at a comparatively low drain voltage. As a result, the electric field in the drain offset diffusion region 2 is alleviated, so that high breakdown voltage characteristics can be obtained. In addition, when the same high breakdown voltage characteristics are to be maintained, comparing with the case where the low concentration buried diffusion region 3 is not provided, the concentration of impurities in the drain offset diffusion region 2 can be increased, so that the ON resistance of the insulated gate transistor can be reduced.
In the structure shown in FIG. 13, the drain offset diffusion region 2 is depleted except the portion near the drain diffusion region 4, so that the equipotential lines in the drain offset diffusion region 2 are distributed uniformly. In particular, in the vicinity of the surface, the distribution of the equipotential lines is substantially perpendicular to the horizontal direction.
Next, FIG. 14 shows a current path when the transistor is conductive. The current coming from the drain electrode 14 flows into the drain diffusion region 4, and then flows through the drain offset diffusion region 2. The current flowing through the drain offset diffusion region 2 flows along two paths, namely, the upper layer portion and the lower layer portion that are divided by the low concentration buried diffusion region 3 buried in the drain offset diffusion region 2. After the divided currents are met and merged into one, the current flows into the source diffusion region 5 through a channel region formed immediately below the gate electrode 11 on the semiconductor substrate 1. Then, the upper layer portion in the drain offset diffusion region 2 has a higher concentration of impurities and a lower specific resistance than those of the lower layer portion, so that most of the current flows in the upper layer portion. Therefore, the amount of the current flowing in the upper layer portion having a high concentration of impurities is an important factor to reduce the ON resistance (the resistance between the source and the drain when the transistor is conductive) of the insulated gate transistor.
However, for example, when the above-described conventional high breakdown voltage semiconductor device is operated at a high temperature of an ambient temperature of 150xc2x0 C. while a high voltage of 500 V or more, such as 600 V, is applied to the metal electrode 14 for the drain, the ON resistance (the resistance between the source and the drain when the transistor is conductive) is increased. This phenomenon can be reproduced by performing a high temperature bias test, which is a life test, and when the voltage applied to the metal electrode 14 for the drain is increased, the change in the ON resistance becomes significant. On the other hand, when the applied voltage is dropped, the change in the On resistance becomes small.
The mechanism of the change in the ON resistance in a high temperature bias test cannot be clarified, and it only can be inferred. One of such inference is as follows.
In general, a semiconductor chip is sealed with a resin for sealing so as to prevent water content from penetrating the resin package. However, novolak epoxy resin used commonly as the resin for sealing contains 0.9% to 1.6% of hydroxyl (OH) groups, and when the hydroxyl groups are activated at a high temperature, the resin 10 for sealing, which is generally regarded as an insulator, becomes semi-insulative (conductive at a high resistance).
In the high breakdown voltage semiconductor device, in general, a semiconductor chip is molded with the resin 10 for sealing, and a plurality of external terminals (not shown) are connected to a plurality of pads (not shown) on the semiconductor chip with metal wires (not shown). To these metal wires, 0 V, which is a ground voltage, 600 V, which is a power source voltage, and a control signal are applied, and therefore when the resin 10 for sealing becomes semi-insulative for the above-described reason, it is inferred that an intermediate voltage between 600 V and 0 V is applied to the surface of the surface protective film 9. Depending on the layout of the semiconductor chip, the resin 10 for sealing positioned on the insulated gate transistor can be of an intermediate voltage of about 100 V, when for example, a pad for ground (not shown) is provided on the side of the insulated gate transistor of the semiconductor chip, and a pad for a power source (not shown) is provided in a position apart from the pad for ground. Taking this into consideration, assuming that the interface between the surface protective film 9 and the resin for sealing 10 of the semiconductor chip is of a potential of 100 V during a high temperature bias test, the inventors of the present invention examined the potential distribution that can be obtained in this case.
Hereinafter, the potential distribution in a high temperature bias test will be described with reference to FIG. 15. FIG. 15 is a view showing a conceivable potential distribution during a high temperature bias test at a high temperature under the same bias conditions as those described with reference to FIG. 14. In FIG. 15, the broken lines indicate equipotential lines.
As shown in FIG. 15, the potential at the interface between the surface protective film 9 and the resin 10 for sealing is of 100 V during the high temperature bias test, so that the equipotential lines of 100 V or less on the surface of the drain offset diffusion region 2 are inclined to the source side, and the equipotential lines of more than 100 V are inclined to the drain side. The inclination of the equipotential lines of more than 100 V to the drain side means that the potential on the oxide film 7 side is negative with respect to the surface of the n-type drain offset diffusion region 2 at the interface between the n-type drain offset diffusion region 2 and the oxide film 7.
In addition, it is reported that when the potential on the oxide film side becomes negative in a high temperature atmosphere at the interface between the semiconductor region and the oxide film, bonds such as Sixe2x80x94H and Sixe2x80x94OH at the interface are broken, and positive fixed charges are generated (xe2x80x9cReliable Technique of Semiconductor Devicexe2x80x9d published by Union of Japanese Scientists and Engineers). When positive fixed charges are generated at the interface between the drain offset diffusion region 2 and the oxide film 7 by such a phenomenon, negative movable charges also are generated in the oxide film 7. Then, the negative movable charges in the oxide film 7 are attracted to the positive high potential of the metal electrode 14 for a drain over time, and a large number of negative charges are distributed near the metal electrode 14 for a drain in the oxide film 7. The negative movable charges that have moved near the metal electrode 14 for a drain in the oxide film 7 are distributed at the interface between the oxide film 7 and the drain offset diffusion region 2, because the equipotential lines in the oxide film 7 are inclined to the drain side. The portion where the negative movable charges were present before the movement is turned into a region where a large number of positive fixed charges are distributed.
In other words, since a large number of negative charges are present at the interface in the oxide film 7 near the metal electrode 14 for a drain, holes in the drain offset diffusion region 2 are attracted thereto, so that the surface of the drain offset diffusion region 2 is inversed to a p-type and becomes a p-type inversion layer 23. On the other hand, in the region where the positive fixed charges remain, electrons in the drain offset diffusion region 2 are attracted thereto, so that the electron density is high locally in the drain offset diffusion region 2. As a result, an n-type accumulated layer 24 is generated in the vicinity of the surface of the drain offset diffusion region 2. Thus, the p-type inversion layer 23 and the n-type accumulated layer 24 are generated in the surface of the drain offset diffusion region 2. The p-type inversion layer 23 narrows the current path in the upper layer in the drain offset diffusion region 2. As a result, it seems that the ON resistance is increased over time.
Therefore, with the foregoing in mind, it is a main object of the present invention to provide a high breakdown voltage semiconductor device having high reliability in which the ON resistance is not deteriorated even if the semiconductor device is used at a high temperature.
A high breakdown voltage semiconductor device of the present invention includes a semiconductor layer of a first conductivity type; a drain offset diffusion region of a second conductivity type formed in the semiconductor layer of the first conductivity type; a source diffusion region of the second conductivity type formed in the semiconductor layer of the first conductivity type apart from the drain offset diffusion region; a drain diffusion region of the second conductivity type formed in the drain offset diffusion region; a buried diffusion region of the first conductivity type that is buried in the drain offset diffusion region and at least a part of which is electrically connected to the semiconductor layer of the first conductivity type; a gate insulating film formed on a portion of the semiconductor layer of the first conductivity type that is positioned between the source diffusion region and the drain offset diffusion region; a gate electrode formed on the gate insulating film; a field insulating film formed on the drain offset diffusion region; at least one plate electrode in a floating state formed on the field insulating film; an interlayer insulating film formed on the field insulating film and the at least one plate electrode; and a metal electrode that is formed on the interlayer insulating film positioned on the at least one plate electrode and a part of which is electrically connected to the drain diffusion region and that is capacitively coupled to the at least one plate electrode.
In one embodiment of the present invention, the drain diffusion region is formed in the central portion of the drain offset diffusion region, and has a substantially circular shape when viewed from the normal direction of the semiconductor layer, the source diffusion region is formed in the semiconductor layer with a predetermined distance from the outer circumference of the drain offset diffusion region so as to surround the outer circumference thereof, and the buried diffusion region is buried in the drain offset diffusion region so as to surround the substantially circular outer circumference of the drain diffusion region.
In one embodiment of the present invention, a plurality of annular electrodes that are formed concentrically around the drain diffusion region as its center are used as the at least one plate electrode.
In one embodiment of the present invention, the metal electrode comprises a plurality of annular metal electrodes positioned on the plurality of annular electrodes via the interlayer insulating film, and a joining portion electrically connecting the plurality of annular metal electrodes to each other, and each of the plurality of annular electrodes is capacitively coupled to the corresponding one of the plurality of annular metal electrodes via the interlayer insulating film.
In one embodiment of the present invention, when viewed from the normal direction of the substrate layer, the metal electrode has a portion covering the entire region up to the outer edge of the annular electrode that is positioned nearest to the drain diffusion region of the plurality of annular electrodes with the drain diffusion region as its center.
In one embodiment of the present invention, the width of the metal electrode positioned above the at least one plate electrode is smaller than that of the at least one plate electrode.
In one embodiment of the present invention, when viewed from the normal direction of the substrate layer, the metal electrode has a portion extended so as to cross a part of the at least one plate electrode on the interlayer insulating film.
In one embodiment of the present invention, the high breakdown semiconductor device further includes a surface protective film formed on the metal electrode and the interlayer insulating film, and a sealing resin portion formed on the surface protective film.
In one embodiment of the present invention, the semiconductor layer is a semiconductor substrate.
In one embodiment of the present invention, the semiconductor layer of the first conductivity type is formed on an insulating substrate.
According to the present invention, at least one plate electrode in a floating state formed on a field insulating film, and a metal electrode that is capacitively coupled to the at least one plate electrode and a part of which is electrically connected to the drain diffusion region. Therefore, positive fixed charges and negative movable charges can be suppressed from being generated at the interface between the drain offset diffusion region and the field insulating film. As a result, a highly reliable high breakdown voltage semiconductor device in which the ON resistance is not changed during a high temperature bias reliability test can be provided.